(1) Field of the Invention
The present invention relates to the manufacture of integrated circuits in general, and in particular, to the design and use of copper interconnections with barrier and adhesion improvements therein.
(2) Description of the Related Art
As the material of choice shifts more and more to copper for forming interconnections in integrated circuits, the relatively poor adhesion of copper to surf aces in general, and its diffusion into other materials, such as silicon, specifically, pose significant reliability problems. An improved method of forming copper interconnections overcoming these problems is disclosed later in the embodiments of the present invention.
Aluminum alloys are the most commonly used conductive materials. However, with the advent of very and ultra large scale integrated (VLSI and ULSI) circuits, the device dimensions have been continually shrinking. Thus, it has become more and more important that the metal conductors that form the interconnections between devices as well as between circuits in a semiconductor have low resistivities for faster signal propagation. Copper is often preferred for its low resistivityxe2x80x94 about 40% less than that of aluminumxe2x80x94 as well as for resistance to electromigration and stress voiding properties. Unfortunately, however, copper suffers from high diffusivity in common insulating materials such as silicon oxide, and oxygen-containing polymers. This can cause corrosion of the copper with the attendant serious problems of loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the circuitry. A copper diffusion barrier is therefore often required.
Conventionally, the various metal interconnect layers in a semiconductor substrate are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate. It will be observed that patterning, that is, photolithography and etching of metal layers to form the needed interconnects constitute a significant portion of the process steps of manufacturing semiconductor substrates, and it is known that both photolithography and etching are complicated processes. It is desirable, therefore, to minimize such process steps, and a process known as dual damascene, provides such an approach. The term xe2x80x98damascenexe2x80x99 is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar.
In a single damascene process, shown in FIG. 1a, grooves (20) are formed in an insulating layer (30) and filled with metal to form conductive lines. Reference numeral (40) in FIG. 1a refers to a plug that had been formed at a previous step to provide the connection to the lower level metal line (50) on substrate (10). Dual damascene (FIG. 1b) takes the process one step further in that, in addition to forming the groove (20) of a single damascene, the conductive hole opening (40xe2x80x2) is also formed in the insulating layer. The resulting composite structure of groove and hole are filled with metal simultaneously. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers. With copper as the conductive metal in groove (20) and/or opening (40xe2x80x2), copper diffuses (shown with arrows (5) in the same Figures) into the surrounding dielectric material (30), causing electrical shorts with other neighboring lines (not shown), or into the underlying silicon (10), causing transistor poisoning where junction leakage occurs with reduced channel mobility in the transistor, thereby destroying the device.
In prior art, methods have been devised to prevent copper diffusion by employing a barrier between the copper interconnect and adjacent materials of the semiconductor device. Bai, et al., in U.S. Pat. No. 5,714,418 show a cross-section of a substrate (10) as in FIG. 1c, upon which a barrier (60) and a copper layer (70) are formed. Barrier (60) comprises a material which impedes the diffusion of copper from copper layer (70) into the underlying substrate (10). However, barrier (60) is not perfect as it has micro-defects such as pinholes (67) or voids in the film, and the barrier further comprises a number of grain boundaries illustrated as (61), (63), (65) and (69). Micro-defect (67) along with grain boundaries, act as weak spots in the barrier, permitting copper from copper layer (70) to diffuse (5) through to the underlying substrate (10). As shown, within micro-defect region (67) the copper of copper layer (70) comes into direct contact with substrate (10). Substrate (10) comprises silicon and silicon dioxide, through which copper rapidly diffuses from the micro-defect in the barrier, particularly at elevated temperatures. Similarly, copper rapidly diffuses along grain boundaries of the barrier when subjected to elevate temperatures.
It is common practice that to better isolate copper layer (70) from the underlying substrate (10), the thickness of barrier (60) is increased. However, increasing the thickness of the barrier also increases the resistance of the resulting copper interconnect as illustrated in FIG. 1d. FIG. 1d shows a cross-section of a substrate (10) upon which an electrical interconnect comprising copper layer (90) and barrier (80) have been formed in a dielectric layer material (95). As shown, the thickness of barrier layer (80) is large in comparison to the thickness of copper layer (90). It is necessary for barrier (80) to be thick enough to adequately prevent diffusion (5) of copper from copper layer (90) into either dielectric material (95) or substrate (10).
Forming a thicker barrier reduces copper diffusion through micro-defect because the defects are more likely to be incorporated into the bulk of the barrier, thereby reducing diffusion paths through the defect. In addition, while a thicker barrier may still comprise grain boundaries leading from the upper to lower surface of the barrier, these boundaries are necessarily longer. Because the grain boundaries are long, it takes a longer time for copper to diffuse throughout the length of these longer grain boundaries. However, increasing the barrier thickness while maintaining the overall width of the interconnect increases the total resistance of the electrical interconnect due to the reduction in volume that the low resistance copper material can occupy. The barrier materials, such as nitrides, are invariably much more resistive than copper. The total width of the interconnect could be increased to counteract the increased resistance, but doing so would reduce the density of the integrated circuit. As a result, the speed at which the integrated circuit operates is reduced.
Thus, Bai, et al., disclose a thin diffusion barrier which permits the low resistivity of copper or other interconnect material to be exploited in an electrical interconnect. In order to achieve a thin diffusion barrier, a bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conducive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.
Chan, et al., in U.S. Pat. No. 5,744,376 disclose a method of manufacturing copper interconnect with a top barrier layer. In this method, a damascene copper connector is formed whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded. Out-diffusion of copper from the connector is prevented by two barrier layers. One is located at the interface between the connector and the insulating layer, while the second barrier is an insulating layer which covers the upper surface of the connector. The damascene process involves filling a trench in the surface of the insulator with copper and then removing the excess by chemical-mechanical polishing. Since the photoresist is never in direct contact with the copper the problem of copper oxidation during resist ashing has been effectively eliminated.
Another method of forming a barrier layer is disclosed by Ngan, et al., in U.S. Pat. No. 5,882,399 which enables a consistently highly oriented crystalline structure in a metallic interconnect. In order to ensure the consistent crystal orientation content of the barrier layer structure, the first layer of the barrier layer structure is formed to have a minimal thickness of at least 150 xc3x85 to compensate for irregularities in the crystal orientation which may be present during the initial deposition of this layer.
Joshi, et al., of U.S. Pat. 5,889,328 teach the forming of refractory metal capped low resistivity metal conductor lines and vias which are not scratched, corroded, or smeared during chemical-mechanical polishing. Zhang, et al., on the other hand, use a conductive film comprising refractory metal and nitrogen in a first portion that lies closer to the substrate and a second portion that lies further from the substrate. The nitrogen percentage for the second portion is lower than the nitrogen atomic percentage for the first portion. The second conductive film, underlying the first conductive film, includes mostly copper. The combination of the first and second portions within the first conductive film provides a good diffusion barrier (first portion) and has good adhesion (second portion) with the second conductive film. In another U.S. Pat. No. 5,814,557, Venkatraman, et al., a barrier layer is used to serve as a seed layer to prevent the out diffusion of copper in a damascene structure.
It is disclosed later in the embodiments of the present invention a method of combining an ion metal plasma (IMP) deposition method with chemical vapor deposition (CVD) of ternary compounds, whereby a thin barrier layer is formed between copper and surrounding materials to promote copper adhesion, while discouraging copper diffusion in integrated circuit interconnects.
It is therefore an object of the present invention to provide a method of forming a damascene copper interconnect in an integrated circuit.
It is another object of the present invention to provide a method of improving the adhesion of copper to the surrounding material in a damascene interconnect.
It is yet another object of the present invention to provide a method of reducing copper diffusion to the surrounding material in a damascene interconnect.
It is still another object of this invention to provide a method of forming a copper interconnect by combining ion metal plasma (IMP) deposition method with PVD/CVD deposition method.
These objects are accomplished by providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a metal layer formed thereon; forming an inter level dielectric (ILD) layer over said substrate; patterning and etching said ILD layer to form a trench with inside walls therein; performing in-situ PVD/CVD deposition of a diffusion barrier layer along with ion metal plasma (IMP) deposition of an adhesion layer to form a combined (adhesion+barrier) layer on said substrate including inside walls of said trench; forming a metal seed layer over said substrate including over said (adhesion+barrier) layer; forming a metal layer over said substrate including over said metal seed layer; and removing excess metal layer from said substrate.